d532b26c9dee0fb5b2186572f921b1e413963ec2
cpu_check_irqs - handle SOFTINT register TICK and STICK timer bits - only check interrupt levels greater than PIL value - handle preemption by higher level traps cpu_exec - handle CPU_INTERRUPT_HARD only if interrupts are enabled - PIL 15 is not special level on sparcv9 Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Read the documentation in qemu-doc.html. Fabrice Bellard.
Description
A QEMU emulator for legacy Apple devices
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