4700a316df7d2cdcd256dcd64a10cec643f4dfa1
The PIIX datasheet says that "before another INIT pulse can be generated via [port 92h], [bit 0] must be written back to a zero. This bug is masked right now because a full reset will clear the value of port 92h. But once we implement soft reset correctly, the next attempt to enable the A20 line by setting bit 1 (and leaving the others untouched) will cause another reset. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org - QEMU team
Description
A QEMU emulator for legacy Apple devices
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