From 91d588c670e54b79eb0263def5b2cb545d4d3338 Mon Sep 17 00:00:00 2001 From: Patrick Babb <72764527+patrickbabb@users.noreply.github.com> Date: Tue, 18 Mar 2025 22:01:55 -0500 Subject: [PATCH] Update spinlock_gcc_arm.hpp Added logic to use LSE as a primary instead of Swap. --- .../smart_ptr/detail/spinlock_gcc_arm.hpp | 27 ++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/Boost/boost/smart_ptr/detail/spinlock_gcc_arm.hpp b/Boost/boost/smart_ptr/detail/spinlock_gcc_arm.hpp index 7d7c78698..95a27a587 100644 --- a/Boost/boost/smart_ptr/detail/spinlock_gcc_arm.hpp +++ b/Boost/boost/smart_ptr/detail/spinlock_gcc_arm.hpp @@ -29,11 +29,30 @@ public: { int r; + #if defined(__ARM_FEATURE_LSE) + // Use LSE atomic instructions if supported + #pragma message("LSE feature detected") // This will print a message in your build logs __asm__ __volatile__( - "swp %0, %1, [%2]": - "=&r"( r ): // outputs - "r"( 1 ), "r"( &v_ ): // inputs - "memory", "cc" ); + "ldaxr %0, [%1];" // Load-Exclusive instruction + "cbnz %0, 1f;" // If the value is non-zero, the lock is already acquired + "stlxr %w0, %2, [%1];" // Store-Exclusive instruction + "cbnz %w0, 1f;" // If the store failed, retry + "mov %0, #0;" // Success, zero indicates lock acquired + "1:" + : "=&r"(r) + : "r"(&v_), "r"(1) + : "memory", "cc" + ); + #else + // Fallback for systems that don't support LSE + #pragma message("LSE feature not detected") // This will print a message in your build logs if LSE is not detected + __asm__ __volatile__( + "swp %0, %1, [%2];" // Swap instruction (used as a fallback) + : "=&r"(r) // output constraint + : "r"(1), "r"(&v_) // input constraints + : "memory", "cc" // clobbered registers + ); + #endif return r == 0; }