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Bin Meng 79a412891f target/riscv: gdbstub: Fix dynamic CSR XML generation 
Since commit 605def6eee ("target/riscv: Use the RISCVException enum for CSR operations")
the CSR predicate() function was changed to return RISCV_EXCP_NONE
instead of 0 for a valid CSR, but it forgot to update the dynamic
CSR XML generation codes in gdbstub.

Fixes: 605def6eee ("target/riscv: Use the RISCVException enum for CSR operations")
Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-24 05:00:12 -07:00
..
alpha
hw/core: Constify TCGCPUOps
2021-05-26 15:33:59 -07:00
arm
bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
2021-06-16 14:33:52 +01:00
avr
hw/core: Constify TCGCPUOps
2021-05-26 15:33:59 -07:00
cris
hw/core: Constify TCGCPUOps
2021-05-26 15:33:59 -07:00
hexagon
hw/core: Constify TCGCPUOps
2021-05-26 15:33:59 -07:00
hppa
tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode
2021-06-19 08:51:11 -07:00
i386
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210619-2' into staging
2021-06-22 10:39:16 +01:00
m68k
tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode
2021-06-19 08:51:11 -07:00
microblaze
hw/core: Constify TCGCPUOps
2021-05-26 15:33:59 -07:00
mips
target/mips: Fix 'Uncoditional' typo
2021-06-05 21:28:54 +02:00
nios2
target/nios2: fix page-fit instruction count
2021-06-05 21:17:10 +02:00
openrisc
hw/core: Constify TCGCPUOps
2021-05-26 15:33:59 -07:00
ppc
tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode
2021-06-19 08:51:11 -07:00
riscv
target/riscv: gdbstub: Fix dynamic CSR XML generation
2021-06-24 05:00:12 -07:00
rx
hw/core: Constify TCGCPUOps
2021-05-26 15:33:59 -07:00
s390x
target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstub
2021-06-21 08:48:21 +02:00
sh4
hw/core: Constify TCGCPUOps
2021-05-26 15:33:59 -07:00
sparc
docs: fix references to docs/devel/tracing.rst
2021-06-02 06:51:09 +02:00
tricore
hw/core: Constify TCGCPUOps
2021-05-26 15:33:59 -07:00
xtensa
hw/core: Constify TCGCPUOps
2021-05-26 15:33:59 -07:00
meson.build
Drop the deprecated unicore32 target
2021-05-12 18:20:52 +02:00