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Suraj Jitindar Singh f0ec31b1e2 target/ppc: Add SPR TBU40 
The spr TBU40 is used to set the upper 40 bits of the timebase
register, present on POWER5+ and later processors.

This register can only be written by the hypervisor, and cannot be read.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-5-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17 10:39:48 +11:00
..
alpha
target/alpha: fetch code with translator_ld
2019-10-28 15:12:38 +00:00
arm
target/arm: ensure we use current exception state after SCR update
2019-12-16 10:52:58 +00:00
cris
cputlb: ensure _cmmu helper functions follow the naming standard
2019-10-28 15:12:38 +00:00
hppa
target/hppa: fetch code with translator_ld
2019-10-28 15:12:38 +00:00
i386
target/i386: disable VMX features if nested=0
2019-12-06 12:35:40 +01:00
lm32
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' into staging
2019-08-22 10:31:21 +01:00
m68k
target/m68k: fetch code with translator_ld
2019-10-28 15:12:38 +00:00
microblaze
target/microblaze: Plug temp leak around eval_cond_jmp()
2019-11-12 16:35:26 +01:00
mips
target/mips: Refactor handling of vector compare 'less than' (signed) instructions
2019-10-25 18:37:01 +02:00
moxie
hw/core: Move cpu.c, cpu.h from qom/ to hw/core/
2019-08-21 13:24:01 +02:00
nios2
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' into staging
2019-08-22 10:31:21 +01:00
openrisc
target/openrisc: fetch code with translator_ld
2019-10-28 15:12:38 +00:00
ppc
target/ppc: Add SPR TBU40
2019-12-17 10:39:48 +11:00
riscv
target/riscv: Remove atomic accesses to MIP CSR
2019-11-14 09:53:28 -08:00
s390x
s390x/tcg: clear local interrupts on reset normal
2019-12-14 10:25:50 +01:00
sh4
target/sh4: fetch code with translator_ld
2019-10-28 15:12:38 +00:00
sparc
target/sparc: Define an enumeration for accessing env->regwptr
2019-11-06 13:35:25 +01:00
tilegx
tcg: TCGMemOp is now accelerator independent MemOp
2019-09-03 08:30:38 -07:00
tricore
tcg: TCGMemOp is now accelerator independent MemOp
2019-09-03 08:30:38 -07:00
unicore32
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' into staging
2019-08-22 10:31:21 +01:00
xtensa
target/xtensa: fetch code with translator_ld
2019-10-28 15:12:38 +00:00