189 lines
7.0 KiB
C
189 lines
7.0 KiB
C
#ifndef HW_ARM_ATV4_PMGR_H
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#define HW_ARM_ATV4_PMGR_H
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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enum boot_device {
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BOOT_DEVICE_NOR = 0,
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BOOT_DEVICE_SPI,
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BOOT_DEVICE_NAND,
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BOOT_DEVICE_NVME,
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BOOT_DEVICE_USBDFU,
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BOOT_DEVICE_TBTDFU,
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BOOT_DEVICE_XMODEM,
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};
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#define TYPE_ATV4_PMGR "atv4.pmgr"
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#define TYPE_ATV4_PMGR_VOLMAN "atv4.pmgr.volman"
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#define TYPE_ATV4_PMGR_PS "atv4.pmgr.ps"
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#define TYPE_ATV4_PMGR_GFX "atv4.pmgr.gfx"
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#define TYPE_ATV4_PMGR_ACG "atv4.pmgr.acg"
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#define TYPE_ATV4_PMGR_CLK "atv4.pmgr.clk"
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#define TYPE_ATV4_PMGR_CLKCFG "atv4.pmgr.clkcfg"
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#define TYPE_ATV4_PMGR_SOC "atv4.pmgr.soc"
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#define TYPE_ATV4_PMGR_PLL "atv4.pmgr.pll"
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#define TYPE_ATV4_PMGR_SCRATCH "atv4.pmgr.scratch"
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#define TYPE_ATV4_PMGR_PWRGATE "atv4.pmgr.pwrgate"
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OBJECT_DECLARE_SIMPLE_TYPE(ATV4PMGRState, ATV4_PMGR)
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#define NUM_PLLS 0x6
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#define rPMGR_CPU0_PS 0x00000
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#define rPMGR_CPU1_PS 0x00008
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#define rPMGR_CPM_PS 0x00040
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#define rPMGR_LIO_PS 0x00100
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#define rPMGR_IOMUX_PS 0x00108
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#define rPMGR_AIC_PS 0x00110
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#define rPMGR_DEBUG_PS 0x00118
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#define rPMGR_DWI_PS 0x00120
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#define rPMGR_GPIO_PS 0x00128
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#define rPMGR_MCA0_PS 0x00130
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#define rPMGR_MCA1_PS 0x00138
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#define rPMGR_MCA2_PS 0x00140
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#define rPMGR_MCA3_PS 0x00148
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#define rPMGR_MCA4_PS 0x00150
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#define rPMGR_PWM0_PS 0x00158
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#define rPMGR_I2C0_PS 0x00160
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#define rPMGR_I2C1_PS 0x00168
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#define rPMGR_I2C2_PS 0x00170
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#define rPMGR_I2C3_PS 0x00178
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#define rPMGR_SPI0_PS 0x00180
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#define rPMGR_SPI1_PS 0x00188
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#define rPMGR_SPI2_PS 0x00190
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#define rPMGR_SPI3_PS 0x00198
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#define rPMGR_UART0_PS 0x001a0
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#define rPMGR_UART1_PS 0x001a8
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#define rPMGR_UART2_PS 0x001b0
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#define rPMGR_UART3_PS 0x001b8
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#define rPMGR_UART4_PS 0x001c0
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#define rPMGR_UART5_PS 0x001c8
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#define rPMGR_UART6_PS 0x001d0
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#define rPMGR_UART7_PS 0x001d8
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#define rPMGR_UART8_PS 0x001e0
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#define rPMGR_AES0_PS 0x001e8
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#define rPMGR_SIO_PS 0x001f0
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#define rPMGR_SIO_P_PS 0x001f8
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#define rPMGR_HSIC0PHY_PS 0x00200
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#define rPMGR_HSIC1PHY_PS 0x00208
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#define rPMGR_ISPSENS0_PS 0x00210
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#define rPMGR_ISPSENS1_PS 0x00218
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#define rPMGR_PCIE_REF_PS 0x00220
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#define rPMGR_ANP_PS 0x00228
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#define rPMGR_MCC_PS 0x00230
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#define rPMGR_MCU_PS 0x00238
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#define rPMGR_AMP_PS 0x00240
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#define rPMGR_USB_PS 0x00248
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#define rPMGR_USBCTLREG_PS 0x00250
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#define rPMGR_USB2HOST0_PS 0x00258
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#define rPMGR_USB2HOST0_OHCI_PS 0x00260
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#define rPMGR_USB2HOST1_PS 0x00268
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#define rPMGR_USB2HOST1_OHCI_PS 0x00270
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#define rPMGR_USB2HOST2_PS 0x00278
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#define rPMGR_USB2HOST2_OHCI_PS 0x00280
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#define rPMGR_USB_OTG_PS 0x00288
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#define rPMGR_SMX_PS 0x00290
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#define rPMGR_SF_PS 0x00298
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#define rPMGR_CP_PS 0x002a0
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#define rPMGR_DISP1_PS 0x002c8
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#define rPMGR_ISP_PS 0x002d0
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#define rPMGR_MEDIA_PS 0x002d8
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#define rPMGR_MSR_PS 0x002e0
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#define rPMGR_JPG_PS 0x002e8
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#define rPMGR_VDEC0_PS 0x002f0
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#define rPMGR_VENC_CPU_PS 0x00300
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#define rPMGR_PCIE_PS 0x00308
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#define rPMGR_PCIE_AUX_PS 0x00310
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#define rPMGR_ANS_PS 0x00318
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#define rPMGR_GFX_PS 0x00320
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#define rPMGR_SEP_PS 0x00400
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#define rPMGR_VENC_PIPE_PS 0x01000
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#define rPMGR_VENC_ME0_PS 0x01008
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#define rPMGR_VENC_ME1_PS 0x01010
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#define rPMGR_MCU_FIXED_CLK_CFG 0x00000
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#define rPMGR_MCU_CLK_CFG 0x00004
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#define rPMGR_MIPI_DSI_CLK_CFG 0x00008
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#define rPMGR_NCO_REF0_CLK_CFG 0x0000c
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#define rPMGR_NCO_REF1_CLK_CFG 0x00010
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#define rPMGR_NCO_ALG0_CLK_CFG 0x00014
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#define rPMGR_NCO_ALG1_CLK_CFG 0x00018
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#define rPMGR_HSICPHY_REF_12M_CLK_CFG 0x0001c
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#define rPMGR_USB480_0_CLK_CFG 0x00020
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#define rPMGR_USB480_1_CLK_CFG 0x00024
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#define rPMGR_USB_OHCI_48M_CLK_CFG 0x00028
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#define rPMGR_USB_CLK_CFG 0x0002c
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#define rPMGR_USB_FREE_60M_CLK_CFG 0x00030
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#define rPMGR_SIO_C_CLK_CFG 0x00034
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#define rPMGR_SIO_P_CLK_CFG 0x00038
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#define rPMGR_ISP_C_CLK_CFG 0x0003c
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#define rPMGR_ISP_CLK_CFG 0x00040
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#define rPMGR_ISP_SENSOR0_REF_CLK_CFG 0x00044
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#define rPMGR_ISP_SENSOR1_REF_CLK_CFG 0x00048
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#define rPMGR_VDEC_CLK_CFG 0x0004c
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#define rPMGR_VENC_CLK_CFG 0x00050
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#define rPMGR_VID0_CLK_CFG 0x00054
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#define rPMGR_DISP0_CLK_CFG 0x00058
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#define rPMGR_DISP1_CLK_CFG 0x0005c
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#define rPMGR_AJPEG_IP_CLK_CFG 0x00060
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#define rPMGR_AJPEG_WRAP_CLK_CFG 0x00064
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#define rPMGR_MSR_CLK_CFG 0x00068
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#define rPMGR_AF_CLK_CFG 0x0006c
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#define rPMGR_LIO_CLK_CFG 0x00070
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#define rPMGR_MCA0_M_CLK_CFG 0x00074
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#define rPMGR_MCA1_M_CLK_CFG 0x00078
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#define rPMGR_MCA2_M_CLK_CFG 0x0007c
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#define rPMGR_MCA3_M_CLK_CFG 0x00080
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#define rPMGR_MCA4_M_CLK_CFG 0x00084
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#define rPMGR_SEP_CLK_CFG 0x00088
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#define rPMGR_GPIO_CLK_CFG 0x0008c
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#define rPMGR_SPI0_N_CLK_CFG 0x00090
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#define rPMGR_SPI1_N_CLK_CFG 0x00094
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#define rPMGR_SPI2_N_CLK_CFG 0x00098
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#define rPMGR_SPI3_N_CLK_CFG 0x0009c
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#define rPMGR_DEBUG_CLK_CFG 0x000a0
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#define rPMGR_PCIE_REF_CLK_CFG 0x000a4
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#define rPMGR_PCIE_APP_CLK_CFG 0x000a8
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#define rPMGR_TMPS_CLK_CFG 0x000ac
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#define rPMGR_MEDIA_AF_CLK_CFG 0x000b0
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#define rPMGR_ISP_AF_CLK_CFG 0x000b4
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#define rPMGR_GFX_AF_CLK_CFG 0x000b8
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#define rPMGR_ANS_C_CLK_CFG 0x000bc
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#define rPMGR_ANC_LINK_CLK_CFG 0x000c0
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#define rPMGR_S0_CLK_CFG 0x10208
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#define rPMGR_S1_CLK_CFG 0x1020c
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#define rPMGR_S2_CLK_CFG 0x10210
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#define rPMGR_S3_CLK_CFG 0x10214
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#define rPMGR_ISP_REF0_CLK_CFG 0x10218
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#define rPMGR_ISP_REF1_CLK_CFG 0x1021c
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#define rPMGR_VOLMAN_CTL 0x0
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#define rPMGR_MISC_ACG 0x0
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#define rPMGR_CLK_DIVIDER_ACG_CFG 0x0
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#define rPMGR_GFX_PERF_STATE_CTL 0x0
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#define rPMGR_SOC_PERF_STATE_CTL 0x0
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#define rPMGR_PLL_EXT_BYPASS_CTL 0x4
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#define PMGR_PLL_BYP_ENABLED (1 << 31)
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#define PMGR_PLL_EXT_BYPASS (1 << 0)
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typedef struct ATV4PMGRState {
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SysBusDevice busdev;
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MemoryRegion pll_iomem;
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MemoryRegion volman_iomem;
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MemoryRegion ps_iomem;
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MemoryRegion gfx_iomem;
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MemoryRegion acg_iomem;
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MemoryRegion clk_iomem;
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MemoryRegion clkcfg_iomem;
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MemoryRegion soc_iomem;
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MemoryRegion scratch_iomem;
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MemoryRegion pwrgate_iomem;
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uint64_t pll_bypass_cfg[6];
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uint64_t scratch[0x4];
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} ATV4PMGRState;
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#endif |