83 lines
2.5 KiB
C
83 lines
2.5 KiB
C
#ifndef HW_ARM_ATV4_H
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#define HW_ARM_ATV4_H
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#include "exec/hwaddr.h"
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#include "hw/boards.h"
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#include "cpu.h"
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#include "hw/intc/apple_aic.h"
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#include "hw/arm/boot.h"
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#include "hw/arm/atv4_chipid.h"
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#include "hw/arm/atv4_pmgr.h"
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#include "hw/arm/atv4_gpio.h"
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#include "hw/arm/atv4_ausb.h"
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#include "hw/arm/atv4_ausb_widget.h"
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#include "hw/arm/atv4_spi.h"
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#include "hw/arm/atv4_anc.h"
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#define TYPE_ATV4 "ATV4"
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#define ATV4_CPREG_VAR_NAME(name) cpreg_##name
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#define ATV4_CPREG_VAR_DEF(name) uint64_t ATV4_CPREG_VAR_NAME(name)
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#define TYPE_ATV4_MACHINE MACHINE_TYPE_NAME(TYPE_ATV4)
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#define ATV4_MACHINE(obj) \
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OBJECT_CHECK(ATV4MachineState, (obj), TYPE_ATV4_MACHINE)
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#define NUM_SPI_PORTS 4
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#define SRAM_LENGTH 0x400000 // 4MB
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// memory addresses
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#define VROM_MEM_BASE 0x100000000
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#define SRAM_MEM_BASE 0x180000000
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#define UNKNOWN2_MEM_BASE 0x202220000
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#define UNKNOWN3_MEM_BASE 0x202240000
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#define PPNNPL_MEM_BASE 0x208081000
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#define ANC0_MEM_BASE 0x208800000
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#define ANC1_MEM_BASE 0x208900000
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#define SPI0_MEM_BASE 0x20a080000
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#define SPI1_MEM_BASE 0x20a084000
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#define SPI2_MEM_BASE 0x20a088000
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#define SPI3_MEM_BASE 0x20a08C000
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#define AUSB_MEM_BASE 0x20c000000
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#define AUSB_WIDGET_MEM_BASE 0x20c900000
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#define PMGR_MEM_BASE 0x20e000000
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#define AIC_MEM_BASE 0x20e100000
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#define GPIO_MEM_BASE 0x20e300000
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#define PMGR_PLL_MEM_BASE (PMGR_MEM_BASE)
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#define PMGR_CLKCFG_MEM_BASE (PMGR_MEM_BASE + 0x10000)
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#define PMGR_CLK_MEM_BASE (PMGR_MEM_BASE + 0x10308)
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#define PMGR_SOC_MEM_BASE (PMGR_MEM_BASE + 0x1a000)
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#define PMGR_GFX_MEM_BASE (PMGR_MEM_BASE + 0x1c200)
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#define PMGR_PS_MEM_BASE (PMGR_MEM_BASE + 0x20000)
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#define PMGR_PWRGATE_MEM_BASE (PMGR_MEM_BASE + 0x22000)
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#define PMGR_VOLMAN_MEM_BASE (PMGR_MEM_BASE + 0x23000)
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#define PMGR_SCRATCH_MEM_BASE (PMGR_MEM_BASE + 0x29000)
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#define PMGR_ACG_MEM_BASE (PMGR_MEM_BASE + 0x32000)
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#define CHIPID_MEM_BASE 0x20e02a000
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typedef struct {
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MachineClass parent;
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} ATV4MachineClass;
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typedef struct {
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MachineState parent;
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AddressSpace *nsas;
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qemu_irq **irq;
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ARMCPU *cpu;
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AppleAICState *aic_state;
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ATV4ChipIDState *chipid_state;
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ATV4PMGRState *pmgr_state;
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ATV4GPIOState *gpio_state;
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ATV4AUSBState *ausb_state;
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ATV4AUSBWidgetState *ausb_widget_state;
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ATV4SPIState *spi_state[4];
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ATV4ANCState *anc0_state;
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ATV4ANCState *anc1_state;
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ATV4_CPREG_VAR_DEF(REG0);
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ATV4_CPREG_VAR_DEF(REG1);
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ATV4_CPREG_VAR_DEF(REG2);
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ATV4_CPREG_VAR_DEF(REG3);
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ATV4_CPREG_VAR_DEF(REG4);
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} ATV4MachineState;
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#endif |