target/mips: Move TCG source files under tcg/ sub directory
To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-29-f4bug@amsat.org>
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@@ -608,4 +608,4 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
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#include "tcg/sysemu_helper.h.inc"
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#endif /* !CONFIG_USER_ONLY */
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#include "msa_helper.h.inc"
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#include "tcg/msa_helper.h.inc"
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@@ -82,9 +82,6 @@ extern const int mips_defs_number;
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int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
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#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
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@@ -151,12 +148,6 @@ struct CPUMIPSTLBContext {
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} mmu;
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};
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void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
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void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
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void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
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@@ -209,8 +200,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
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return r;
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}
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void mips_tcg_init(void);
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void msa_reset(CPUMIPSState *env);
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/* cp0_timer.c */
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@@ -1,11 +1,3 @@
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gen = [
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decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'),
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decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
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decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
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decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
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decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
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]
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mips_user_ss = ss.source_set()
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mips_softmmu_ss = ss.source_set()
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mips_ss = ss.source_set()
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@@ -20,35 +12,12 @@ if have_system
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subdir('sysemu')
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endif
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mips_tcg_ss = ss.source_set()
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mips_tcg_ss.add(gen)
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mips_tcg_ss.add(files(
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'dsp_helper.c',
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'exception.c',
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'fpu_helper.c',
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'ldst_helper.c',
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'lmmi_helper.c',
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'msa_helper.c',
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'msa_translate.c',
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'op_helper.c',
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'rel6_translate.c',
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'translate.c',
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'translate_addr_const.c',
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'txx9_translate.c',
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))
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mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files(
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'tx79_translate.c',
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), if_false: files(
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'mxu_translate.c',
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))
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if 'CONFIG_TCG' in config_all
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subdir('tcg')
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endif
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mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
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mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss])
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target_arch += {'mips': mips_ss}
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target_softmmu_arch += {'mips': mips_softmmu_ss}
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target_user_arch += {'mips': mips_user_ss}
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@@ -1,3 +1,32 @@
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gen = [
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decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'),
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decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
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decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
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decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
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decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
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]
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mips_ss.add(gen)
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mips_ss.add(files(
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'dsp_helper.c',
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'exception.c',
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'fpu_helper.c',
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'ldst_helper.c',
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'lmmi_helper.c',
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'msa_helper.c',
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'msa_translate.c',
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'op_helper.c',
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'rel6_translate.c',
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'translate.c',
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'translate_addr_const.c',
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'txx9_translate.c',
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))
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mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
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'tx79_translate.c',
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), if_false: files(
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'mxu_translate.c',
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))
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if have_user
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subdir('user')
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endif
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@@ -11,15 +11,21 @@
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#define MIPS_TCG_INTERNAL_H
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#include "tcg/tcg.h"
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#include "exec/memattrs.h"
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#include "hw/core/cpu.h"
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#include "cpu.h"
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void mips_tcg_init(void);
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void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
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void mips_cpu_do_interrupt(CPUState *cpu);
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bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
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bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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const char *mips_exception_name(int32_t exception);
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@@ -46,6 +52,11 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb);
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hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
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MMUAccessType access_type, uintptr_t retaddr);
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void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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void cpu_mips_tlb_flush(CPUMIPSState *env);
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#endif /* !CONFIG_USER_ONLY */
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