target/avr: CPU class: Add GDB support

This includes GDB hooks for reading from wnd wrtiting to AVR
registers, and xml register definition file as well.

[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Co-developed-by: Michael Rolnik <mrolnik@gmail.com>
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[thuth: Fixed avr_cpu_gdb_read_register() parameter]
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-7-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Rolnik authored and Philippe Mathieu-Daudé committed 2020-07-10 17:58:32 +02:00
1 parent 3fa28dd6cf
commit 12b3540547
5 files changed
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<?xml version="1.0"?>
<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!-- Register numbers are hard-coded in order to maintain backward
compatibility with older versions of tools that didn't use xml
register descriptions. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.cpu">
<reg name="r0" bitsize="8" type="int" regnum="0"/>
<reg name="r1" bitsize="8" type="int"/>
<reg name="r2" bitsize="8" type="int"/>
<reg name="r3" bitsize="8" type="int"/>
<reg name="r4" bitsize="8" type="int"/>
<reg name="r5" bitsize="8" type="int"/>
<reg name="r6" bitsize="8" type="int"/>
<reg name="r7" bitsize="8" type="int"/>
<reg name="r8" bitsize="8" type="int"/>
<reg name="r9" bitsize="8" type="int"/>
<reg name="r10" bitsize="8" type="int"/>
<reg name="r11" bitsize="8" type="int"/>
<reg name="r12" bitsize="8" type="int"/>
<reg name="r13" bitsize="8" type="int"/>
<reg name="r14" bitsize="8" type="int"/>
<reg name="r15" bitsize="8" type="int"/>
<reg name="r16" bitsize="8" type="int"/>
<reg name="r17" bitsize="8" type="int"/>
<reg name="r18" bitsize="8" type="int"/>
<reg name="r19" bitsize="8" type="int"/>
<reg name="r20" bitsize="8" type="int"/>
<reg name="r21" bitsize="8" type="int"/>
<reg name="r22" bitsize="8" type="int"/>
<reg name="r23" bitsize="8" type="int"/>
<reg name="r24" bitsize="8" type="int"/>
<reg name="r25" bitsize="8" type="int"/>
<reg name="r26" bitsize="8" type="int"/>
<reg name="r27" bitsize="8" type="int"/>
<reg name="r28" bitsize="8" type="int"/>
<reg name="r29" bitsize="8" type="int"/>
<reg name="r30" bitsize="8" type="int"/>
<reg name="r31" bitsize="8" type="int"/>
<reg name="sreg" bitsize="8" type="int"/>
<reg name="sp" bitsize="8" type="int"/>
<reg name="pc" bitsize="8" type="int"/>
</feature>